Data platforms and pipelines
Event-driven ingestion on AWS, streaming and batch processing on Databricks and BigQuery, all defined in Terraform with CI/CD behind it.
I'm Liam Warner. Through Bumble Bytes I design, build and run data pipelines, machine-learning services and backend systems. For the past year I've been on contract to a Fortune 500 media company, and I also develop formally verified FPGA image-processing IP.

Most projects need more than one specialism. Bumble Bytes covers the whole lifecycle: design and estimates, build, deployment, and handover to your team.
Event-driven ingestion on AWS, streaming and batch processing on Databricks and BigQuery, all defined in Terraform with CI/CD behind it.
Audio and video ML services: training-data tooling, labelling and review apps, model training and model-serving APIs, connected to the systems that use them.
Node.js, TypeScript and Python services, payments and authentication, test automation, and the pipelines that keep releases routine.
Verilog image-processing IP with machine-checked proofs, signed off on AMD, Altera and Lattice parts and tested on Cyclone V hardware. I also run the same flow on other people's FPGA blocks, as a fixed-price sign-off and verification service.
RankFilter IPRecent contract and permanent roles. BSc Computer Science (3D Games), First-Class Honours, Sheffield Hallam University.
Alongside client work, Bumble Bytes builds its own products.
Median, percentile and defect-pixel-correction cores for FPGA and ASIC video. A 5×5 median needs 52 comparators per pixel where column sharing, the lowest published count we know of, needs 63, and the cores use 75 % fewer LUTs than AMD's free Vitis median filter in the same flow. Every network is proved correct in Lean 4, and the cores run on Altera Cyclone V silicon.
Product page and demoTurns any image into Game Boy or Game Boy Color graphics that respect the hardware's palette and tile limits, ready for GB Studio.
Live demo SourceAn opinionated MVC framework for Node.js in the style of Laravel, with CLI scaffolding, an event system and cron-style timers.
SourceRemote contract engagements, fixed-price FPGA sign-off and verification, and licences for the RankFilter FPGA and ASIC IP. Send a short description of the work and I'll reply with availability and next steps.
[email protected]For contract work, FPGA IP evaluation or anything else, email is quickest.
RankFilter has its own page with a live demo video, measured results on three FPGA families and a downloadable product brief.
RankFilter FPGA IP